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Human time is currently the most valuable resource that is available to a manager in charge of an embedded system design and realization project. Furthermore, it is also the most expensive and the scarcest, if compared to the other resources involved in the design and realization process.
Nevertheless, though accurate and exhaustive theory and tools have been designed to estimate the number of gates used, or the occupied silicon area (and therefore the projectís cost), the timing features (and therefore each componentís speed), and the power consumption, surprisingly, when it comes to estimating the development effort, i.e. the cost of the human resources, no such theory and tools are available.
The widespread availability of intellectual property components provided by dedicated suppliers, makes now possible to virtually acquire any type of standardized components required by the embedded system industry, at a price which is well-known and, most important, known in advance. Despite this, no formal methodology is available to estimate the cost of an internally developed component, thus being any make or buy comparison virtually impossible. That cost will not be known before the project is completed, and at that time, all the costs will be entirely occurred and all the decisions taken.
The object of this thesis is to provide a method for estimating the number of lines of VHDL code in which an embedded system design project will evolve Ėand therefore its expected development cost and time, given its specifications. Specifications will not be provided in a distinct specification language but in VHDL itself: the designer will just start the development of the project by writing a set of VHDL files containing a draft of the architectures and packages he plan to use. He can proceed in a development by refinement way, and as the draft approaches the completed project, estimates will converge to the actual value of the completed project size in lines of code. The basic idea is that every estimate comes with a confidence interval, and any additional information available supplied by the designer reduces its the width.