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(This page contains material related to my thesis at Politecnico.)
POLITECNICO DI MILANO
Facoltà di Ingegneria
Corso di Laurea in Ingegneria Informatica

A DEVELOPMENT EFFORT AND SIZE ESTIMATION METHOD FOR PARTIALLY AND FULLY SPECIFIED VHDL PROJECTS.

(UNA METODOLOGIA DI STIMA DELLA DIMENSIONE E DELLO SFORZO DI SVILUPPO PER PROGETTI VHDL PARZIALMENTE E COMPLETAMENTE SPECIFICATI.)

By: Daniele Paolo Scarpazza
Advisor: Prof. Fabio Salice
Co-advisor: Prof. William Fornaciari

Full thesis, in english. Includes full text, illustrations and tables; features PDF bookmarks), available a PDF file.

Download it here (zipped PDF file, 5.68M).

If you have not Adobe Acrobat Reader, get it free at www.adobe.com/acrobat.

The same thesis as above is also available without bookmarks and hyperrefs. Since some people think this is better-looking when printed, I made that available too.

Download it here (zipped PDF file, 5.62M).

Thesis presentation, available in OpenOffice Impress (sxi) format (italian language only); presentazione della tesi in lingua italiana, disponibile in formato OpenOffice Impress (sxi).

Download sxi file (zip not required, 2.06M).

This is the official version of the presentation. If you have not OpenOffice installed, get it free at www.openoffice.org.

Thesis presentation, available in Microsoft Office PowerPoint (ppt) format (italian language only); presentazione della tesi in lingua italiana, disponibile in formato PowerPoint di Microsoft Office (ppt).

Download ppt file (zipped, 1.71M)

This file is given only for compatibility towards Microsoft Office users. The official version is the OpenOffice one.

Complete tuning and validation project base.

Download archive file (tar-gzipped, 3.06M)

This archive contains all the project files belonging to the projects used to tune and validate the models and the methodology presented in the thesis. Please refer to part III (page 95 and following) of the thesis to learn more on the composition and use of the project base.

Abstract:

Human time is currently the most valuable resource that is available to a manager in charge of an embedded system design and realization project. Furthermore, it is also the most expensive and the scarcest, if compared to the other resources involved in the design and realization process.

Nevertheless, though accurate and exhaustive theory and tools have been designed to estimate the number of gates used, or the occupied silicon area (and therefore the projectís cost), the timing features (and therefore each componentís speed), and the power consumption, surprisingly, when it comes to estimating the development effort, i.e. the cost of the human resources, no such theory and tools are available.

The widespread availability of intellectual property components provided by dedicated suppliers, makes now possible to virtually acquire any type of standardized components required by the embedded system industry, at a price which is well-known and, most important, known in advance. Despite this, no formal methodology is available to estimate the cost of an internally developed component, thus being any make or buy comparison virtually impossible. That cost will not be known before the project is completed, and at that time, all the costs will be entirely occurred and all the decisions taken.

The object of this thesis is to provide a method for estimating the number of lines of VHDL code in which an embedded system design project will evolve Ėand therefore its expected development cost and time, given its specifications. Specifications will not be provided in a distinct specification language but in VHDL itself: the designer will just start the development of the project by writing a set of VHDL files containing a draft of the architectures and packages he plan to use. He can proceed in a development by refinement way, and as the draft approaches the completed project, estimates will converge to the actual value of the completed project size in lines of code. The basic idea is that every estimate comes with a confidence interval, and any additional information available supplied by the designer reduces its the width.

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The above document was last modified on 2004-04-16 14:34:02; page last updated on 2010-07-02 at 21:22:34.
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thesis-200209242110

(last update: 2010 Jul 02)
thesis-200209242110

Contents:

 
LogoPolitecnico.png File : LogoPolitecnico.png 8735 bytes 2002-10-16
 
pdf.png File : pdf.png 3529 bytes 2002-10-16
 
present.png File : present.png 9759 bytes 2002-10-16
 
Presentazione-tesi.zip File : Presentazione-tesi.zip 1.71 Mbytes 2002-10-16
 
sourcetree+validation-20020822.tar.gz File : sourcetree+validation-20020822.tar.gz 3.06 Mbytes 2002-08-22
 
src.png File : src.png 9215 bytes 2002-10-17
 
tab.gif File : tab.gif 41 bytes 2001-08-20
 
thesis-200209240626.zip File : thesis-200209240626.zip 5.63 Mbytes 2002-09-24
 
thesis-200209242110.zip File : thesis-200209242110.zip 5.68 Mbytes 2002-09-24

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